# 基于FPGA新型步进电机控制器硬件实现外文翻译.doc

1111111111111 . 核准通过，归档资料。 未经允许，请勿外传！ 基于 FPGA 新型步进电机控制器硬件实现 Daniel Carrica, Senior Member, IEEE, Marcos A. Funes, and Sergio A. González, Member, IEEE 摘要 ：本文提出了一种新颖的基于现场可编程门阵列的步进电机控制器，这种控制器呈现出了显著的优势。 该系统提供了一种新型算法和可编程逻辑的组合，以达到硬件工作既高速又精确。 关键字 ：现场可编程门阵列（ FPGA ） ，运动控制，步进电机。 Ⅰ .引言 在高精 度 步进电机应用 中 ，使用小 步距 电动机是 非常 必要的 ， 其尺寸 是由实际需求决定的 。另一个 可供 选择 的技术 是 微步 技术，其 电机 步长通过控制进一步 的 减 小 。 由于微步 与 很小的位移有关， 因此必须由 大量 微步求得 总位移。 而总位移必须在可接受的时间内执行。因此，微步之间的时间差应该尽量减小。 当 以微步 的运作方式 分度时，控制器和驱动器之间的高速数据传输是必须的。 此外，开环编码器比那些闭环编码器要便宜的多，如果选择开环系统，则必须使用速度分布图，以避免失去步进功能的后果。 图 1 显示 了 一台 步进 电机 的基本构成 。 它有三个部分 ： 1）速度分布图生成器； 2)分度器 ；3)电流驱动装置 。 (1)和 (2)被置 在了 我 们称之为 控制器 的里面 。 9JWKffwvG#tYM*Jg 2) the indr; and 3) the power drivers. Blocks (1) and (2) are embedded in what we named controller. After velocity profiles are generated, they have to be translated into pulse intervals by the indr. Each index pulse means that the motor must increment its rotor position in one step/microstep, hence the name indr. This block functions as a velocity-to-time translator. This block is unique to the commanding of incremental motion devices since other types of motors can be commanded just by applying the velocity profile in of current or voltage [1], [2]. 1111111111111 . Fig. 1. Complete control system. The implementation of the controller of Fig. 1 can be pered by two alternatives: off-line or on-line schemes. A. Off-Line In the off-line schemes the timing of the steps/microsteps is calculated prior the movement [3], [4]. The velocity profile and the time space between pulses are calculated and then stored in some kind of memory media bundled into the hardware, i.e., ROM or even hard drives. A disadvantage of these schemes is that they require an important hardware volume, composed of memories and timers. This volume is proportional to the quantity of motors and the extension and precision of displacements. B. On-Line An intelligent system carries out the operation of calculating the index pulses through a time lagging sequence generation algorithm. In Fig. 2 a flowchart of one basic scheme can be seen. This flowchart contains two main blocks: )(krV construction, where the velocity profile is actually developed, and )(kt calculation, where the time between the current step and the next is calculated. That is, )(krV is the velocity profile generation and )(kt is the indr of Fig. 1. Often a common block is shared because a single equation computes both the velocity profile and the )(kt . For example, (1) and (2) express a typical algorithm for a trapezoidal profile [5]. aNVakNVt k )1(2)1(2 2 2m a x2m a x)( （ 1） )()(1kk tstepV （ 2） where )(krV is the resulting speed, maxV is the maximum speed of the motor, N is the total number of steps or microsteps, a is the acceleration of the trapezoidal profile and )(kt is the time of the k -th step. These schemes as well as the off-line ones make use of timers for obtaining the indd pulses. Since it is necessary one timer per motor, this approach is often discouraged when multiple motors have to be commanded by a single processor. Another important disadvantage is the computing time cT , required 1111111111111 . to compute (1). cT imposes a practical limit to the speed. Moreover, not only Tc but the timer resolution, Tr affect the maximum speed as in (3) cr TTV 1max （ 3） Fig. 2. On-line algorithms. Current timer resolutions are small enough to discard the rT at the equation. Therefore, (3) turns into (4) cTV1max （ 4） Standard algorithms fail to reach high speeds, mainly because the computing time, cT . In order to resolve maxV the goal is to provide a new algorithm with a more effective step generation procedure without timers. II. PROPOSED ALGORITHM The proposed algorithm can be explained as follows. In order to estimate the time )(kt , it is assumed that )(kt is kn times cT , since it is an accurate way of measuring time without using timers. Therefore, the proposed algorithm has to do the following functions during each iteration: 1) Let 1kn 1111111111111 . 2) Assume ckk Tnt )( （ 5） where kn is a positive integer number. Fig. 3. Flow chart of the algorithm. 3) Verify if )(kt assumed allows the wished )(kV . Thus, it means )()(1kkr tV （ 6） where )(krV is the reference velocity at the k -th step. 4) If the verification is true, then cute the new step/microstep. If not, then increment kn and repeat the process. (points 2, 3, and 4) 1 kk nn （ 7） From (5) it can be seen that the resolution of )(kt is cT . The equality in (6) is not possible because of this resolution. Equation (6) becomes the comparison stated in (8) )()(1kkr tV （ 8） Eliminating the division in (8) is mandatory for reducing the iteration time. Therefore a simple contraction as in (9) is preferred 1)()( kkr tV （ 9） 1111111111111 . The new algorithm is based on (5), (7), and (9). cT in (5) has the same meaning as in (4), but with a considerable smaller magnitude, since the computations here are very straightforward. It is experimentaly demonstrated that cT ten times less than in conventional algorithms is achieved. Fig. 4. Intended velocity profile. To conclude, the algorithm consists basically on a periodic accumulative sum until the intended velocity is reached. Fig. 3 shows the flowchart of a system that implements (5), (7) and (9). The velocity profiles block was previously cuted. From (5), )(kt resolution of the new algorithm is cT since kn is an integer. )(kt resolution in the newalgorithm arises to a velocity quantization problem because velocity is the inverse of )(kt (6). Since the term )(kt is a multiple of cT and 1kn , it turns out that the speed commanded has the following characteristics: KnnnKVVVTntVkkkckknk 21,,,2m a x11m a xm a x)(（ 10） 1111111111111 . As an example, Fig. 4 shows a trapezoidal profile which starts at minV and has a maximum maxV . In order to keep track of the intended speed (in discontinuous line), the system commands an initial value of 7kn .This results in an initial speed of 7/maxV which is the closest possible speed to the intended initial speed, minV . At 1t , kn changes to 6. As a consequence a higher speed of 6/maxV occurs. At 2t , 5kn produces a commanded speed of 5/maxV . It then follows that at 6t time the commanding speed is maxV which equals the intended velocity profile. The quantification effect is more remarkable at higher speeds when )(kt times are smaller as cT . The effect can also be explained since intermediate speeds cannot take place between maxV and 2/maxV , or between 2/maxV and 3/maxV , nor among 3/maxV and 4/maxV , etc. Fig. 5. FPGA based control system. Therefore, an algorithm has been developed which requires neither timers nor lookup tables and can work for much higher speeds. It’s disadvantage is the quantification effect which depends on the magnitude of cT . With current DSP technology, a minimum 6cT s is obtainable. This cT magnitude produces a quantification level of 2000 steps at speeds arround 15 000 steps/s, which shows the importance of the problem. III. HARDWARE IMPLEMENTATION In order to reduce the computing time, a hardware implementation is proposed. The algorithm presented in Section II is simple enough to be cuted by a custom hardware. Hardware 1111111111111 . implementation permits multiple parallel tasks, thus, providing an effective way of implementing true parallelism which allows a great reduction of computing time because operations such as the reference profile generation, multipication and indexation can be cuted in separate blocks and can run independently ones of the others. Equations (5) and (9) are replaced by (11) . Although, this means no changes in the algorithm, it reduces the pair of multiplications to only one. This fact allows an efficient hardware implementation without perance demerit. Hardware implementation of (5) and (9) is presented in Fig. 5, where the block diagram of the controller is shown. The COUNTER, wich counts cT clock periods, represents the cution of (5). The hardware implementation of (11) is carried out by the MULTIPLIER and the COMPARATOR ckR TnV1 （ 11） When the inequation is satisfied, a new step is commanded. The signal is then fed to the DRIVER INTERFACE, which commands the pulses to the driver of each motor phase. Fig. 5 shows a four phase motor. The clock period cT of hardware implementation is equivalent to the computing time in the software cution of the algorithm of Section II. The clock period cT defines the time resolution of the controller. As cT can be well reduced in hardware approach, the quantizacion effect on the mechanical velocity will be negligible. Fig. 6. Position and velocity profile with the FPGA based system. Standard implementation of a multiplier is accomplish by acombinatorial structure. This approach is very good regarding the cT time because it presents a minimum delay imposed by the logic gates, but it involves a great number of logic resources, which increase proportionally with the multiplier word length. As an example, a 16 16 bits product requires the 90% of a 10 000 logic gates FPGA [6], [7]. In order to overcome the FPGA area problem, a sequential arquitecture for the multiplier is proposed [8], [9]. This approach allows an effective area reduction of 10 times, but with a greater , cT i.e., 16 clock 1111111111111 . pulses for a 16-bit word multiplier. However, with a 40 MHz clock, cT time is only 400 ns which remains neglicted for system perance. As a consequence, a sequential multiplier was adopted, which permited the implementation of the algorithm in a FPGA of 6000 logic gates. A trapezoidal profile is generated, with several parameters, such as acceleration, minimum and maximum speed, and step quantity. The controller decides how the profile must be based on these parameters, and generates a reference profile to drive the stepper motor. As a conclusion, a new controller based on a novel algorithm implemented by hardware was proposed. The new system provides a good combination to achieve both high speed and high precision motion on a compact hardware. Furthermore, this controller can easily drive full, half and micro-step mode applications due to the flexibility and the reduced computing time with the FPGA implementation. IV. EXPERIMENTAL RESULTS To uate the perance of the system, the developed algorithm was implemented in a Xilinx FPGA XC4006–3. This device can run at synchronous system clock rates up to 80 MHz、 and has a capacity 6000 logic gates. A hybrid stepping motor was used in the experiments. Motor characteristics: 400 step/rev, inertial moment 13·10-7kg·m2， 71033 etT N·m. No aditional load was connected. Fig. 7. Velocity profile with the FPGA based system The position measures were obtained through an incremental optical encoder ELAP-E521 with a resolution of 1024 pulses/rev whose inertial moment is2.5·10－ 6kg·m2. It was coupled through an HELICAL-WA25 with an inertial moment of 2.3·10－ 6kg·m2 . The position curve was obtained by reading the encoder signal with a high resolution timer. The position was off line derived to obtain the speed profile. The muliplier works with a 40-MHz clock rate, which yield a multiplication time of 400 ns. 800cT ns was adopted, wich remains negligible in relation to the motor speed. 1111111111111 . The stepper motor must develop a 12 000 step displacement following a reference trapezoidal profile with charasteristics: 500min V steps/ s, 6000max V steps/ s and a max acceleration 4200max a steps /s . The resultant speed and position profiles can be seen in Fig. 6. The low cT time allows an almost continuous profile and very high speeds, higher than those generated by standard software algorithms. Due to the characteristic of the profile, the stepper motor passes through resonance area [5]. This effect can be observed at low speeds in the profiles. Fig. 7 shows a complete profile obtained at high speeds with full step. Note the continuity at all the effective speed range. Fig. 8 shows a complete profile obtained for a microsteping application. The stepper motor used in this experiment was a SLO-SYN KML093F14C5 whose characteristics are: 200 step/rev, holding torque 816holdT N cm and a rotor inertia 3.32kg·cm2 . The position values were obtained through an optical incremental encoder with a resolution of 500 pulses/rev. The microstep drive module used was an SLO-SYN MD808, configured to produce 2000 pulses/rev. As a consequence, the system must generate a high velocity profile with 500min V steps s, 50000max V steps s and a max acceleration 5000max a steps/ s . The time adopted for the application was 400 ns in order to reduce the speed jumps at maxV to 1000 steps/s, so the speed jump remains under 5% of maxV . This effect can be observed as a ripple component at the top of the profile. Fig. 8. Velocity profile for microsteping application. The system achieved very high speed that was unreachable with standard algorithms cuted by a processor. Furthermore the new controller does not require the timers, wich are necessary in conventional systems, and the processor was replaced by a FPGA of similar size and equivalent cost. 1111111111111 . V. CONCLUSION A novel algorithm with reduced quantity of operations was introduced. This algorithm implemented on FPGA allows a substantial decrease of the equivalent processing time developed by classic velocity controllers. As a consecuence, the stepper motor can reach very high speeds never obtained with standard algorithm based systems. Due to the system architecture, one FPGA can drive several stepper motors simultaneously without increasing the processing time. It can drive three stepper motors with current 6000 gates FPGAs. This advantage make the system very convenient since it allows the increase of the number of motors, simply using a larger FPGA. 1111111111111 . 译 文 评 阅 导师评语 指导教师： 年 月 日